techsimplifiedtv

typedef enum logic [1:0] {
    IDLE = 2'b00,
    READ = 2'b01,
    WRITE = 2'b10
} state_t;
module enum_example;
    state_t current_state;
    initial begin
        current_state = IDLE;  // Start in the IDLE state
        $display("Current State: %s", current_state.name());

techsimplifiedtv

typedef union {
    logic [31:0] full_word;  // Access as a full 32-bit word
    logic [15:0] half_word[2];  // Access as two 16-bit words
    logic [7:0] byte[4];  // Access as four 8-bit bytes
} data_u;
module union_example;
    data_u data;
    initial begin
        data.full_word = 32'hDEADBEEF;  // Set the entire 32-bit value
        $display("Half Word 0: %h, Half Word 1: %h", data.half_word[0], data.half_word[1]);

techsimplifiedtv

typedef struct {
    logic [7:0] address;
    logic [31:0] data;
    logic valid;
} packet_t;
module struct_example;
    packet_t pkt;
    initial begin
        pkt.address = 8'hA5;
        pkt.data = 32'hDEADBEEF;

techsimplifiedtv

typedef logic [31:0] word_t;  // Create an alias for 32-bit logic

module typedef_example;
    word_t data;  // Now, use `word_t` instead of writing `logic [31:0]`
    
    initial begin
        data = 32'hDEADBEEF;
        $display("Data: %h", data);  // Output: Data: DEADBEEF
    end
endmodule

techsimplifiedtv

module int_example;
    int a = 10;  // Signed 32-bit integer
    int b = -5;
    int sum;

    initial begin
        sum = a + b;  // Strong typing makes arithmetic simple
        $display("Sum: %d", sum);  // Output: Sum: 5
    end
endmodule

techsimplifiedtv

//  Define an Interface
interface bus_if(input logic clk);
    logic [7:0] addr;
    logic [7:0] data;
    logic write;

    modport master (output addr, data, write, input clk);
    modport slave (input addr, data, write, input clk);
endinterface
module master(bus_if.master bus);

techsimplifiedtv

interface <interface_name> ([optional input signals]);
    // Declare signals
    logic [7:0] addr;
    logic [7:0] data;
    logic write, read;

    // Define modports (optional)
    modport master (input read, write, output addr, data);
    modport slave (output read, write, input addr, data);

techsimplifiedtv

interface bus_if(input logic clk);
    logic [7:0] addr;
    logic [7:0] data;
    logic write;
    // Modports define signal directions for modules
    modport master (output addr, data, write, input clk);
    modport slave (input addr, data, write, input clk);
endinterface
module master(bus_if.master bus);
    assign bus.addr = 8'hAA;  // Example address

techsimplifiedtv

module master(input clk, output [7:0] addr, output [7:0] data, output write);
    assign addr = 8'hAA;  // Example address
    assign data = 8'h55;  // Example data
    assign write = 1'b1;  // Write enable
endmodule
module slave(input clk, input [7:0] addr, input [7:0] data, input write);
    always @(posedge clk) begin
        if (write)
            $display("Received addr: %h, data: %h", addr, data);
    end

techsimplifiedtv

# Verilog Code (Using `reg` and `wire`):
module counter (
    input clk,
    input reset,
    output reg [3:0] count
);
    wire enable;
    assign enable = (count < 10);
    always @(posedge clk or posedge reset) begin
        if (reset)