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kierdavis / vector.toml
Created May 6, 2022 14:43
Vector config for parsing auditd logs
[sources.audit_raw]
type = "file"
include = [ "/var/log/audit/audit.log" ]
read_from = "beginning"
[transforms.audit_parsed]
type = "remap"
inputs = ["audit_raw"]
source = '''
# The format is deceptively complex - it looks like key-value pairs but there's actually a few layers of nesting.
#!/usr/bin/env python3.7
import sys
import tty
import termios
import subprocess
import re
from pathlib import Path, PurePath
def getch():
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kierdavis / charon_hdl.sv.nw
Created August 10, 2017 19:54
Example of literate SystemVerilog (using noweb)
\chapter{Introduction}
This document explains the reference SystemVerilog implementation of the charon architecture.
\chapter{Core}
This chapter covers the implementation of the core architecture as defined by \todo{reference to architecture spec}. That is, the intrastructure required to transfer data words between abstract ports as dictated by a sequence of instructions in main memory. It does not assign any meaning to the ports.
\section{Top-level structure}

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kierdavis / keybase.md
Created April 21, 2014 21:08
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kierdavis / DCPU-16.v
Created April 19, 2012 17:42
DCPU-16 implementation in Verilog
/*
General state machine operation:
ST_FETCH - Load instruction word
ST_LOADAREF - Decode operand_a into a_type and a_value components
ST_LOADA - Load a using a_type and a_value
ST_LOADB - Decode operand_b and load b
ST_DECODE - Distribute to ST_opcode
ST_opcode - Modify b, using a
ST_STORE - Store b into a's location using a_type and a_value
*/